First, what is an ASIC? An ASIC is an Application Specific Integrated Circuit which basically means that it is an Integrated Circuit on a single piece of silicon and its use is limited to a particular application or function. An example would be an ASIC to process an audio CODEC or run a specific cryptographic function. But why is creating one so difficult?
Cost! From all the tool licensing and the fab costs can reach nearly 1 Million dollars! That is not something the normal maker has on hand. This also does not include the actual engineering cost of designing all the IP that goes into the chip. So what has changed? A new open-source Process Development Kit from Google and Skywater and the OpenLane ASIC tools from Efabless was released. This allowed anyone to get started designing their own ASICs. But what about the fabrication costs? Well, those are still expensive but not to the same degree since there are now options to share designs on the same silicon wafer being produced. These are called Shuttles and there is even a free one based on a lottery system.
Hackaday Supercon Tiny Tapeout Class
I had heard about these developments since it is closely related to my line of work FPGA development. But didn’t really have the opportunity until last year’s Hackaday Supercon where I was able to sign up for a workshop introduction to the open ASIC tools and the Tiny Tapeout project.
TinyTapeout is an educational project that makes it easier and cheaper than ever to get your digital designs manufactured on a real chip!
https://tinytapeout.com/
The Tiny-Tapeout project takes one of the spots of the silicon shuttle and further divides that into smaller designs that build infrastructure to help bring up the design and get started.
This workshop was taught by Matt Venn who also runs the Zero to ASIC online course that does exactly what the name implies, teaching you the basics all the way through using the tools to design your own chip.
Since we only had a few hours at Supercon there was obviously not enough time for the participants to design everything. But we did go through the digital logic tutorials in Wokwi. This browser-based software can be used to simulate a variety of hardware but we were using it to connect up logic gates and flip flops.
Wokwi is an online Electronics simulator. You can use it to simulate Arduino, ESP32, and many other popular boards, parts and sensors.
https://docs.wokwi.com/
But once you have the circuit designed using the Wokwi components you can submit the design to the Tiny-Tapeout project by forking their template repo, adding the Wokwi ID to the documentation, and running two GitHub actions that run a design rules check, then creating the ASIC block.
But what do I want to build, I couldn’t go too crazy as there is a space and IO limitation that makes processing a challenge.
Tiny-Tapeout Constraints
The design constraints in the Tiny-Tapeout ASIC are pretty limiting when compared to the enormous design space of traditional ASICs but we are just starting so it’s good to have some limitations. First is the IO constraint, we are limited to 8 input pins and 8 output pins, this includes any control and clock signals that our design might need. Next is the area constraint, each design was recently increased to 150 x 170 um for Tiny-Tapeout 2. This is approximately enough for 1000 logic gates.
My ASIC Design Part 1
I decided to take on an ambitious design that I could use to test out my digital logic design and signal processing skills, so I decided to try building an FIR filter! An FIR filter is a Finite Impulse Response filter that is used everywhere in Digital Signal Processing (DSP). They are used to create low pass, high pass, and bandpass filters performing signal conditioning before other signal processing functions.
Due to the space and io constraints, I could not design a very useful FIR filter but it was a good exercise in digital design and kept me interested in completing the project by the deadline!
Building Blocks
My design methodology was to build incremental blocks of digital logic that I could then chain together into the larger functionality of a filter. This is because I needed to do several math functions like adding and multiplying.
I decided to create a 4-bit 2-tap FIR filter, this fits within the original size constraints and takes advantage of the full 8-bit output. This leaves inputs for a clock signal, three selection signals that we need to allow loading of the filter taps and testing, and then four inputs for tap and signal data.
In the Wokwi logic options, we don’t have an adder block but we do have basic and, or, nor, xor, etc gates. These can be connected together to make a full adder circuit that takes in 2 bits (and a carry bit) and outputs the sum (and a carry bit) shown in the circuit diagram below.
These adder instances can be chained together through the carry signal to create the 4-bit adder that we need for the filter.
binary-adder-and-subtractor Logic Reference
To create the multiplier logic needed to multiply the Tap with the incoming signal I used the adder design with and gates replicating the circuit below.
4-by-4-bit-multiplier Logic Reference
Then in order to combine the output from the two tap multiplications I created an 8-bit adder by extending the carry chain of 2 4-bit adders.
That’s most of the mathematical functions taken care of, but there is more to implementing a filter than just math. We need control logic to correctly feed the mathematical functions with data to operate on.
For an FIR filter, we need a way to store the multiplication tap weights that influence the type of filter that we want to process the incoming data. This means that we need our circuit to store data, but up until this point we have only been using logic gates to process high or low values, how do we make these store data?
This is done using what is commonly known as a flip-flop shown in its primitive, where data is loaded into it via an enable signal.
Thankfully we don’t need to replicate this logic in Wokwi, as there is a flip-flop component.
This is pretty good but in order to load the taps one at a time without overwriting them I decided to add a modification to data storage by adding a second flip-flop and a nor gate on the enable into the first element.
So what does this do? it makes the data available on the output dependent on the enable signal change so when it goes from high to low or low to high. this can then be chained with a pulse generator to create a reliable loading mechanism that can be tied to a clock.
Now we also need to implement a delay line that feeds each of the taps with the input signal data. this can be accomplished with just a simple set of flip-flops as we don’t need the complex loading mechanism.
After creating all of the digital processing logic I also needed to think about how I was going to test the hardware functionality when I ultimately receive my design in hardware. For this, I decided to multiplex several signals so that I could easily test the functional blocks in the design like the multiply operation independent of the rest of the filter.
You can check out the design on Wokwi and play around with it at the link below
https://wokwi.com/projects/347894637149553236
After completing the whole design I then needed to create my submission to the Tiny-Tapeout project. This was done by forking the GitHub template submission using GitHub actions. The whole process was detailed in a video on the Tiny-Tapeout project.
https://github.com/Tschucker/tt02-submission-tiny-fir
Once completed you should be able to see a really cool graphic of the ASIC metal layers of the design.
To submit your design to Tiny-Tapeout you need to link your GitHub repo and pay for the option that you want. When I submitted my design it was $100 for a spot on silicon and to receive a board with the chip on it for testing. If you just wanted your design on the chip it was $20!
My Second ASIC Design Part 2
Thankfully I was able to get my FIR filter design done before the original deadline but because it got extended I started thinking about what other things I could add on since a second design on the same chip was only $20 extra.
I workshopped a few ideas but unfortunately, most were just not possible with the current limitations of the design medium. So I decided to keep it simple and create a PRBS generator. PRBS stands for a pseudorandom binary sequence which in simple terms is a sequence of 1s and 0s that approximate random data. Generating truly random sequences is very difficult but a PRBS can be generated by a simple LFSR circuit.
An LFSR is a linear feedback shift register, which is essentially just a shift register where the input is a linear function of its previous state. This feedback is most commonly created by an XOR of the output of calculated points in the shift register. For more information on PRBS generators using LFSRs check out this great DigiKey article.
PRBS data can also be used as a way to check digital communication links using a principle of the LFSR. In that, the inverted output of one LFSR can be fed into a duplicate logic and can be checked for errors in that data. So if a communication channel introduces errors due to noise the bit error rate can be measured.
Because the LFSR is a mathematical function we can have several variants but I decided to go with a simple PRBS15 format, where there are 15 bits in the shift register. Below is the Wokwi design, where we have two LFSRs where the output is looped back into the input externally.
This simulation also includes a logic analyzer so we can plot the output in GTKWave!
From the top we can see the input clock on D0, then the PRBS15 output on D1, next is the PRBS15 checker output error on D2, and lastly the PRBS15 checker raw output on D3. The checker starts throwing errors at first but once it locks on the error signal remains zero for the entire simulation as there are no errors introduced.
You can check out this design submission at my other GitHub link below.
https://github.com/teaandtechtime/tt02-submission-prbs15
Tiny-Tapeout 2
A bit more information on Tiny-Tapout 2 which is specific to the run my designs is on.
Check out the full list of designs that went into this Tiny-Tapout run, there is even a datasheet with descriptions of how to interact with the designs that all submissions included! So not only can you run your own design when you get the chip you can try out the others as well.
https://tinytapeout.com/runs/tt02/
Next Steps
Now that the design has been submitted to the fab we just have to wait for the chips and the Tiny-Tapeout boards to be delivered. I will post updates when I get my board and see if things work!
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